Verifying IP for Hard Disk Drives

A leading manufacturer of hard disk drives for enterprise, desktop, mobile computing and consumer electronics applications uses blocks of intellectual property (IP) in its next-generation disk controller application specific integrated circuits (ASICs). Some of these IP blocks are used in several different products, making it an imperative that designs be exhaustively verified under all possible operating conditions prior to release.

In the past, the manufacturers' ASIC designers relied on digital simulation as their primary means of verifying IP blocks. They also employed automatic constrained pseudo-random testbench generation to construct thousands of different combinations of commands and data packets. Early in the design of a new compute-intensive IP block, the design architects calculated that it would take approximately 500 CPU-years to simulate all the test cases necessary to test this particular design. With a six month design schedule, it was clear that simulation alone would not be adequate. That's when the designers decided to evaluate several hardware-assisted verification platforms. This proved to be the ideal solution for delivering a quality product within the tight design schedule. In this case, the hard disk drive manufacturer selected EVE's ZeBu-ZV platform.

The IP design presented unique verification challenges. The block had a 32-bit interface, over which commands and data were loaded into the block using a packet-based protocol. Once set up, it then processed the data for about four seconds of real time, after which it presented the results over the same 32-bit interface. At an operating speed of 150 MHz, four seconds represented 600,000,000 cycles. The design team needed to run several hundred thousand of these test cases to fully verify the design.

On this project, a digital simulator/testbench generator combination was used for initial verification runs to prove basic functionality, using about 50 tests per command. Once this verification methodology was generally functional, the designers switched to the combination of the hardware-assisted verification platform and testbench generator, which enabled them to run thousands of tests for each command.

To maximize performance, synthesizable transactors were used as the interface between the testbench code on the PC and the emulated IP block in the verification platform. Transactors performed the conversion from high-level commands and data packets to bit-level signals using the hardware-assisted verification platform. The SCE-MI standard from Accellera defined how the transactors were written. They consist of an application program interface (API) on the software side to exchange high-level packets or messages, and a synthesizable bus-functional model (BFM) or state machine mapped onto the hardware platform.

To further accelerate simulation, the design team took advantage of a property of this particular IP block: The only interaction between the testbench and the IP block occurred during the initial setup of the test and the downloading of results at the end of the run. In between these two interactions, the design executed a large number of cycles with no external communication. The designers exploited this by making the verification platform run in lock-step mode with the testbench generator only during these interactions, and switching to a 15MHz clock supplied by the verification platform in between these accesses. To implement this solution, they changed the main clock of the design to switch between two inputs: the clock coming from testbench generation and a clock generated by the verification platform's on-board clock generator.

Using this hybrid approach, the testbench generator produced each new command and data combination, and then transferred the packet through a C function-call to the verification platform transactors. The testbench generator then switched the verification tool to the fast clock and initiated the test. It was able to run the tests at 15 MHz, equivalent to 1/10 of real time. In 40 seconds, the test would finish and it would signal the testbench generator that it was ready to present the result.

Meanwhile, the testbench generator was computing the expected results in software, using the same algorithms implemented in the IP block. Once the hardware-assisted verification platform and the testbench generator completed their respective runs, they would compare their results and flag any differences that occurred as errors.

The design team was surprised that with the first exposure to the system it took them only two hours to get their IP block compiled into the verification platform and running correctly. With a few more weeks of effort, the team had implemented and debugged the transactor interface and had the system running at 15 MHz.

In the first few days, the designers identified 25-30 new bugs in the design, which had escaped detection using simulation without hardware-assistance. In the five weeks to follow, they ran the hardware-assisted verification platform 24 hours per day, 7 days per week, generating hundreds of thousands of additional test cases. Through these runs, they found four additional bugs that were obscure corner cases related to specific sequences of commands. These bugs would have surfaced during product testing, but would have necessitated ASIC respins at a cost of $500,000 or more.

The designers of this hard disk drive manufacturer plans to continue running additional test cases on their hardware-assisted verification platform 24x7 until the resource is needed for another project. Since it takes only one hour per week to kick off new jobs and check the results of the previous runs, there is little reason not to run the additional tests for added confidence. Their hardware-assisted verification platform has become the keystone of their design strategy.

Article Source:- http://www.edadesignline.com/showArticle.jhtml?articleID=192200261

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